library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sd_card_controller is
port (
clk		:	in std_logic;
write		:	in std_logic;
read		:	in std_logic;
chipselect	:	in std_logic;
address		:	in unsigned(7 downto 0);
writedata	:	in unsigned(31 downto 0);
readdata	:	out unsigned(31 downto 0);

CARD_CLK	:	out std_logic;
CARD_CMD	:	out std_logic;
CARD_DAT	:	in  std_logic;
CARD_SD3	:	out std_logic
);
end sd_card_controller;

architecture card of sd_card_controller is
begin

  CardClk : process (clk)
  begin
	if clk'event and clk = '1' then
      if chipselect = '1' then
        if write = '1' then
          CARD_CLK <= writedata(0);
        end if;
      end if;
	end if;
  end process CardClk;

  DataIn : process (clk)
  begin
    if clk'event and clk ='1' then
      if chipselect = '1' then
        if write = '1' then
          CARD_CMD <= writedata(0);
        end if;
      end if;
    end if;
  end process DataIn;

  DataOut : process (clk)
  begin
    if clk'event and clk ='1' then
      if chipselect = '1' then
        if read = '1' then
          readdata(0) <= CARD_DAT;
        end if;
      end if;
    end if;
  end process DataOut;

  Ncs : process (clk)
  begin
    if clk'event and clk = '1' then
      if chipselect = '1' then
        if write = '1' then
          CARD_SD3 <= writedata(0);
        end if;
      end if;
    end if;
  end process Ncs;

end architecture card;